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I C R O C LOC K
MK1574 Frame Rate Communications PLL
Description
The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to the 8 kHz backplane clock, simplifying clock generation and distribution in communications systems. MicroClock can customize this device for any other different frequencies.
Features
* Packaged in 16 pin narrow (150 mil) SOIC * Exact multiplications stored in the device eliminate the need for external dividers * Accepts 8 kHz input clock * Output clock rates include T1, E1, T2, E2 * 3.0V to 5.5V operation * Available in commercial (0 to +70 C) or industrial (-40 to +85 C) temperature ranges * For jitter attenuation, use the MK2049
Block Diagram
VDD GND
2
2
Output Buffer Output Buffer Output Buffer Output Buffer
CLK1 CLK2 CLK3 8kHz (recovered)
4 FS0-3 8kHz Input Clock
Input Buffer
PLL Clock Synthesis and Control Circuitry
CAP1
CAP2
1 Revision 011999 Printed 11/15/00 MicroClock Division of ICS * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel*(408)295-9818fax
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Pin Assignment
ICLK VDD VDD CAP1 GND CAP2 GND FS0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FS3 N/C FS2 FS1 CLK3 CLK2 CLK1 8KOUT
MK1574 Frame Rate Communications PLL
Output Clocks Decoding Table MK1574-01 (MHz)
Decode Address FS3:0 (Hex) 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 ICLK pin 1 Reserved Reserved Reserved Reserved 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz Multiplier On-chip Reserved Reserved Reserved Reserved 2940 1960 2760 2640 1920 6480 2112 1578 8192 6176 1024 772 CLK 1 pin 10 Reserved Reserved Reserved Reserved 23.52 15.68 22.08 21.12 15.36 51.84 16.896 12.624 65.536 49.408 8.192 6.176 CLK 2 pin 11 Reserved Reserved Reserved Reserved 11.76 7.84 11.04 10.56 7.68 25.92 8.448 6.312 32.768 24.704 4.096 3.088 CLK 3 pin 12 Reserved Reserved Reserved Reserved 5.88 3.92 5.52 5.28 3.84 12.96 4.224 3.156 16.384 12.352 2.048 1.544
16 pin (150 mil) SOIC
* 0 = connect directly to ground, 1 = connect directly to VDD.
Pin Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name ICLK VDD VDD CAP1 GND CAP2 GND FS0 8KOUT CLK1 CLK2 CLK3 FS1 FS2 N/C FS3 Type I P P I P I P I O O O O I I I Description Input clock. Connect to an 8kHz clock input. Connect to +3.3V or +5V. Connect to +3.3V or +5V. Must be same voltage as pin 2. Connect a ceramic capacitor and a resistor in series between this pin and CAP2. Refer to page 4. Connect to ground. Connect a ceramic capacitor and a resistor in series between this pin and CAP1. Refer to page 4. Connect to ground. Frequency Select 0. Determines CLK outputs per table above. Recovered 8kHz output clock. Can be lower jitter, better duty cycle than input clock. Clock 1 determined by status of FS3:0 per table above. Clock 2 determined by status of FS3:0 per table above. Clock 3 determined by status of FS3:0 per table above. Frequency Select 1. Determines CLK outputs per table above. Frequency Select 2. Determines CLK outputs per table above. No Connect. Nothing is connected to this pin. Frequency Select 3. Determines CLK outputs per table above.
Type: I = Input, O = output, P = power supply connection 2 Revision 011999 Printed 11/15/00 MicroClock Division of ICS * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel*(408)295-9818fax
MDS 1574-01 D
I C R O C LOC K
External Components/Crystal Selection
MK1574 Frame Rate Communications PLL
The MK1574 requires a minimum number of external components for proper operation. An RC network (see Capacitor Selection on following page) should be connected between CAP1 and CAP2 as close to the chip as possible. A high quality ceramic capacitor is recommended. A decoupling capacitor of 0.1F must be connected between VDD and GND pins (pins 2 and 3, 5 and 7) close to the chip, and 33 terminating resistors can be used on clock outputs with traces longer than 1 inch.
Electrical Specifications
Parameter Supply Voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Soldering Temperature Storage Temperature Operating Voltage, VDD Input High Voltage, VIH Input Low Voltage, VIL Output High Voltage Output High Voltage Output Low Voltage Operating Supply Current, IDD Short Circuit Current Input Capacitance Input Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle, High Time Absolute Clock Period Jitter Actual mean frequency error versus target, note 2 Conditions Referenced to GND -0.5 0 Max of 10 seconds -65 3 2 IOH=-4mA IOH=-25mA IOL=25mA No Load, VDD=5.0V Each output VDD-0.4 2.4 0.4 15 100 7 8.0000 0.8 to 2.0V 2.0 to 0.8V At VDD/2 Any clock selection 1.5 1.5 60 0 Minimum Typical Maximum 7 VDD+0.5 70 250 150 5.5 0.8 Units V V C C C V V V V V V mA mA pF kHz ns ns % ns ppm
ABSOLUTE MAXIMUM RATINGS (Note 1)
DC CHARACTERISTICS (VDD = 5V unless noted)
AC CHARACTERISTICS (VDD = 5V unless noted)
40
49 to 51 1 0
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. All multipliers as shown in the table on page two are exact, and are stored in ROM on the chip.
3 Revision 011999 Printed 11/15/00 MicroClock Division of ICS * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel*(408)295-9818fax
MDS 1574-01 D
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MK1574 Frame Rate Communications PLL
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have piezoelectric properties allow mechanical vibration in the system to increase the output jitter because the mechanical energy is converted directly to voltage noise on the VCO input. The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components are calculated using the constants K1 and K2 from the table on page 5. The loop bandwidth is set by the capacitor C and the constant K1 using the formula BW (Hz) = K1 C Equation 1
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula R= * K2 C Equation 2; (zeta) is the damping factor
For example, to design the loop filter when generating 8.192 MHz from 8 kHz: 1. From the table on page 2, the address is E. The table on page 5 shows constants K1=0.0516 and K2=6.2. 2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using Equation 1, 400 = 0.0516 C 0.0516 400
Therefore,
C=
(
)
2 = 16.6 nF (16 nF nearest standard value)
3. A good value for the damping factor is 0.707. From Equation 2, R= 0.707 * 6.2 16E-9 = 34.7 k (36 k nearest standard value)
4 Revision 011999 Printed 11/15/00 MicroClock Division of ICS * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel*(408)295-9818fax
MDS 1574-01 D
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Loop Filter Constants
MK1574 Frame Rate Communications PLL
This table shows the constants K1 and K2 that are used with the equations on page 4 to calculate the external loop filter components. Loop Filter Constants for MK1574-01
Decode Address FS3:0 (Hex) 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 Loop Filter Constants K1 K2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0.0430 7.4 0.0527 6.0 0.0444 7.2 0.0454 7.0 0.0533 6.0 0.0410 7.8 0.0508 6.3 0.0587 5.4 0.0365 8.7 0.0420 7.6 0.0516 6.2 0.0594 5.4
PC Board Layout
A proper board layout is critical to the successful use of the MK1574. In particular, the CAP1 and CAP2 pins are very sensitive to noise and leakage (CAP1 at pin 4 is the most sensitive). Traces must be as short as possible and the capacitor and resistor must be mounted next to the device as shown to the right. The capacitor connected between pins 3 and 5 is the power supply decoupling capacitor. The high frequency output clocks on may benefit from a series 33 resistor connected close to the pin (not shown). V
cap cap
G
resist.
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
V =connect to VDD G =connect to GND
Clock Multipliers/Accuracies
In the table on page 2 are the actual multipliers stored in the MK1574 ROM, which yield the exact values shown for the output clocks. 5 Revision 011999 Printed 11/15/00 MicroClock Division of ICS * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel*(408)295-9818fax
MDS 1574-01 D
I C R O C LOC K
Package Outline and Package Dimensions
MK1574 Frame Rate Communications PLL
16 pin SOIC narrow
Symbol A b c D E H e h Q Inches Min Max 0.055 0.070 0.013 0.019 0.007 0.010 0.385 0.400 0.150 0.160 0.225 0.245 .050 BSC 0.016 0.004 0.01 Millimeters Min Max 1.397 1.778 0.330 0.483 0.191 0.254 9.779 10.160 3.810 4.064 5.715 6.223 1.27 BSC 0.406 0.102 0.254
E
H
D Q e b c
h x 45 A
Ordering Information
Part/Order Number MK1574-01S MK1574-01STR MK1574-01SI MK1574-01SITR Marking MK1574-01S MK1574-01S MK1574-01S MK1574-01S Package 16 pin narrow SOIC Add Tape & Reel 16 pin narrow SOIC Add Tape & Reel Temperature 0 to 70C 0 to 70C -40 to +85C -40 to +85C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
CHANGE HISTORY Version Date first published A 1/24/97 B 2/3/98 C 2/23/98 D 1/19/99
Comments Original Added I grade, revised filter equations, updated address. Added Absolute Jitter value. Added additional capacitor requirements.
6 Revision 011999 Printed 11/15/00 MicroClock Division of ICS * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel*(408)295-9818fax
MDS 1574-01 D

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